With the continuous increase of the integration level of semiconductor devices, the critical dimension (CD) of transistors has become smaller and smaller. With the rapid shrinking of the size of the transistors, the thickness of the gate dielectric layer and the working voltage of the transistors are unable to correspondingly change. Thus, the difficulty for preventing the short channel effect is increased; and the leakage current of the transistor is increased.
The fins of fin field-effect transistors (FinFETs) form fork-like three-dimensional (3D) structures like fishes' fins. The channel regions of the FinFETs protrude from the surface of the substrate to form the fins. The gate structures of the FinFETs cover the top and side surfaces of the fins. Thus, the reverse type layers are formed on all sides of the channel regions. Correspondingly, the gate structures are able to control the “on” and “off” of control circuits from two sides of the fins. Such a design (device structure) is able to increase the control ability of the gate structures to the channel regions; and is able to effectively suppress the short channel effect of the FinFETs.
To isolate adjacent fins, before forming the doped source/drain regions, isolation structures are formed in the substrate between adjacent fins. The isolation structures between the doped source/drain regions in different fins need to have a certain height. If the heights of the isolation structures between the doped source/drain regions in different fins are too small, the doped source/drain regions may be easy to connect together; and the performance of the FinFETs are easily affected.
The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.